A typical IC design cycle involves numerous steps ranging generally from initial feasibility studies, functional verification and circuit design through fabrication, packaging and data sheet generation. It is frequently cost effective to conduct tests throughout the design cycle to ensure that the design and the resulting wafers meet certain quality parameters. Various types of testing thus are performed at different stages of the design and fabrication process. An in-line parametric test is an electrical test performed on test pattern structures located on wafers, such as arranged at specific locations on the wafer. The test structures can be utilized to assess film thickness or linewidths as well as to ascertain an indication of leakage current or breakdown voltages or other parameters of transistor devices.
Many different IC failures can also be detected by employing fault models. For example, automatic test pattern generators can be employed to generate patterns that are used to test semiconductor devices after manufacture, and in some cases to assist with determining the cause of failure. The efficacy of the test pattern can be influenced by the fault model under consideration, the type of circuit under test (full scan, synchronous sequential, or asynchronous sequential), the level of abstraction used to represent the circuit under test (gate, register-transistor, switch), and the required test quality. However, many existing testing methods tend to focus on defect-driven yield issues.